The invention relates to television receivers capable of receiving vestigial-sideband amplitude-modulation (VSB) digital television (DTV) signals as used in terrestrial broadcasting in the United States and also capable of receiving quadrature-amplitude-modulation (QAM) digital television signals as used in cablecasting or direct satellite broadcasting (DBS) in the United States.
Receivers for VSB DTV signals are described by C. B. Patel and A. L. R. Limberg in U.S. Pat. No. 5,479,449 issued Dec. 26, 1995 with the title xe2x80x9cDIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER, AS FOR INCLUSION IN AN HDTV RECEIVERxe2x80x9d. In the described receivers the VSB DTV signals are converted to a frequency band just above baseband and are then digitized before being synchrodyned to baseband in the digital regime. The synchrodyning is done using a digital complex multiplier. Hilbert transform filtering responsive to a stream of real samples from the analog-to-digital converter generates a stream of imaginary samples, which stream of imaginary samples together with a delayed stream of the real samples supply a complex multiplicand signal to the complex multiplier. Read-only memory addressed by a sample counter supplies a complex digital carrier wave from sine/cosine look-up tables, which complex digital carrier wave is applied to the complex multiplier as a complex multiplier signal. The product output signal from the complex multiplier comprises as real and imaginary components thereof an in-phase (I) synchronous demodulation signal and a quadrature-phase (Q) synchronous demodulation signal. The I synchronous demodulation signal is descriptive of baseband symbol coding. The Q synchronous demodulation signal is used as a basis for generating automatic frequency and phase control (AFPC) signal of local oscillations supplied to the mixer for converting the VSB DTV signals to the frequency band just above baseband.
The use of infinite-impulse response filters for developing complex multiplicand signal for the digital complex multiplier in DTV receivers of bandpass tracker type is described by C. B. Patel and A. L. R. Limberg in U.S. Pat. No. 5,548,617 issued Aug. 20, 1996, with the title xe2x80x9cDIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING RADER FILTERS, AS FOR USE IN AN HDTV RECEIVERxe2x80x9d. The use of finite-impulse response filters for developing complex multiplicand signal for the digital complex multiplier in DTV receivers of bandpass tracker type is described by C. B. Patel and A. L. R. Limberg in U.S. Pat. No. 08/577,469 issued Dec. 22, 1995 with the title xe2x80x9cDIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING NG FILTERS, AS FOR USE IN AN HDTV RECEIVERxe2x80x9d. QAM/VSB DTV receivers in which receivers both QAM and VSB DTV signals are processed through the same intermediate-frequency amplifiers to generate a final I-F signal are described by C. B. Patel and A. L. R. Limberg in U.S. Pat. No. 5,715,012 issued Feb. 3, 1998 with the title xe2x80x9cRADIO RECEIVERS FOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV SIGNALSxe2x80x9d. The DTV signals are converted to a frequency band just above baseband and are then digitized before being synchrodyned to baseband in the digital regime. The real samples of the digitized final I-F signal are supplied to real-samples-to-complex-samples conversion circuitry to generate complex multiplicand signal for a digital complex multiplier for demodulating QAM DTV signals and for another digital complex multiplier for demodulating VSB DTV signals. The complex multiplier for demodulating QAM DTV signals multiplies the complex multiplicand signal by a complex multiplier signal supplied from sine/cosine look-up tables for the QAM DTV carrier stored in read-only memory addressed by a sample counter. The resulting complex product has a real component and an imaginary component corresponding to the results of in-phase and quadrature-phase synchrodynes to baseband in the digital regime. The complex product is supplied to a symbol synchronizer before symbol decoding. The digital complex multiplier for demodulating VSB DTV signals multiplies the complex multiplicand signal by a complex multiplier signal supplied from sine/cosine look-up tables for the VSB DTV carrier stored in read-only memory addressed by a sample counter, following procedures similar to those disclosed in U.S. Pat. No. 5,479,449. U.S. patent application Ser. No. 5,606,579 issued Feb. 25, 1997 to C. B. Patel and A. L. R. Limberg with the title xe2x80x9cDIGITAL VSB DETECTOR WITH FINAL I-F CARRIER AT SUBMULTIPLE OF SYMBOL RATE, AS FOR HDTV RECEIVERxe2x80x9d and U.S. Pat. No. 5,659,372 issued Aug. 19, 1997 to C. B. Patel and A. L. R. Limberg with the title xe2x80x9cDIGITAL TV DETECTOR RESPONDING TO FINAL-IF SIGNAL WITH VESTIGIAL SIDEBAND BELOW FULL SIDEBAND IN FREQUENCYxe2x80x9d are also of interest. The C. B. Patel et alii patents referred to above are all assigned to Samsung Electronics Co., Ltd., pursuant to employee invention agreements already in force at the time the inventions disclosed in these patents were made.
The complex multipliers described in these patents are constructed of component digital multipliers that generate only a real component of a complex product or only an imaginary component of a complex product. These component digital multipliers can be constructed using multiplier and multiplicand registers and logic circuitry. Such component multipliers have latent delay of several samples, which latent delays introduce undesirable additional delay into the feedback loop(s) that generate automatic frequency and phase control (AFPC) signal of local oscillations supplied to the mixer for converting the DTV signals to the frequency band just above baseband. Using read-only memories (ROMs) storing look-up tables of the products of multiplicand and multiplier signals received as partial (read) addresses, to provide the component digital multipliers of a complex multiplier used in demodulating DTV signals, eliminates latent delay in the component multiplications. This avoids introduction of undesirable additional delay into the AFPC loop(s).
The ROMs used as the component digital multipliers generally take up more area on a monolithic integrated circuit die than do multipliers constructed using multiplier and multiplicand registers and logic circuitry, the inventors observe. So in a QAM/VSB DTV receiver it is desirable, the inventors point out, to use the same complex multiplier for digitally synchrodyning digital intermediate-frequency signal to baseband during both the reception of VSB digital television signals and the reception of QAM digital television signals. Different complex carriers are used as the multiplier input signal during the reception of VSB digital television signals and during the reception of QAM digital television signals.
Using read-only memories (ROMs) storing look-up tables of the products of multiplicand and multiplier signals received as partial (read) addresses, to provide the component digital multipliers of a complex multiplier used in demodulating DTV signals, eliminates latent delay in the component multiplications. This avoids introduction of undesirable additional delay into the AFPC loop that controls the frequency and phase of local oscillations used in converting the DTV signals to the frequency band just above baseband, prior to digitization of the DTV signals and application of the digitized DTV signals to the complex multiplier as multiplicand signal.
A preferred embodiment of the invention in QAM/VSB DTV receivers uses a single digital complex multiplier for demodulating both QAM and VSB DTV signals as received at different times. The component digital multipliers of the complex multiplier are provided by ROMs. The complex digital carriers used by the complex multiplier are supplied from ROMs storing sine/cosine look-up tables for the QAM carrier and for the VSB carrier as translated to the final intermediate-frequency band.